feat(sha256): add sha256d80 backend API and ARM64 kernel entry
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65
sha256/sha256_backend.h
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65
sha256/sha256_backend.h
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#ifndef SHA256_BACKEND_H
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#define SHA256_BACKEND_H
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#include <stdint.h>
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/*
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* Compact SHA256 state: only the 8 chaining words (32 bytes).
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* Avoids copying the bloated OpenSSL SHA256_CTX (~112 bytes) in the hot loop.
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*/
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typedef struct {
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uint32_t h[8];
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} sha256_state_t;
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typedef struct {
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sha256_state_t init_state;
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sha256_state_t first_chunk_state;
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uint8_t block1_template[64];
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uint8_t block2_template[64];
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} sha256d80_midstate_t;
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/* Set state to SHA256 initial values (IV). */
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void sha256_state_init(sha256_state_t *state);
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/* Serialize the 8 state words into a 32-byte big-endian digest. */
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void sha256_state_to_digest(const sha256_state_t *state, uint8_t out[32]);
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/* Single SHA256 block compression (64-byte block). */
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void sha256_transform_fast(sha256_state_t *state, const uint8_t block[64]);
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/*
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* 2-way interleaved SHA256 block compression.
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* Processes two independent (state, block) pairs so the CPU can overlap both
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* instruction chains. On non-ARM builds falls back to two sequential calls.
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*/
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void sha256_transform_fast_2way(
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sha256_state_t *stA, const uint8_t blkA[64],
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sha256_state_t *stB, const uint8_t blkB[64]
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);
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/* Prepare SHA256d(80-byte header) midstate and constant blocks from header[0..75]. */
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void sha256d80_midstate_init(sha256d80_midstate_t *mid, const uint8_t header_76[76]);
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/*
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* Hash 4 consecutive nonces with SHA256d(header80).
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* start_nonce lane order: [n, n+1, n+2, n+3].
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*/
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void sha256d80_hash_4way(
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const sha256d80_midstate_t *mid,
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uint32_t start_nonce,
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sha256_state_t out_states[4]
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);
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/*
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* Hash 4 consecutive nonces and return hit mask against target words.
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* target_words are big-endian words target[0..7].
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* bit i set => lane i meets target.
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*/
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uint32_t sha256d80_scan_4way(
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const sha256d80_midstate_t *mid,
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uint32_t start_nonce,
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const uint32_t target_words[8],
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sha256_state_t out_states[4]
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);
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#endif
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